In order to increase the speed of computer processors, prior art architectures have used dual execution paths for executing instructions. Dual execution path processors can operate according to a single instruction multiple data (SIMD) principle, using parallelism of operations to increase processor speed.
However, despite use of dual execution paths and SHAD processing, there is an ongoing need to increase processor speed. Typical dual execution path processors use two substantially identical channels, so that each channel handles both control code and datapath code. While known processors support a combination of 32-bit standard encoding and 16-bit “dense” encoding, such schemes suffer from several disadvantages, including a lack of semantic content in the few bits available in a 16-bit format.
Furthermore, conventional general purpose digital signal processors are not able to match application specific algorithms for many purposes, including performing specialized operations such as convolution, Fast Fourier Transforms, Trellis/Viterbi encoding, correlation, finite impulse response filtering, and other operations.
In one embodiment according to the invention, there is provided a computer processor having control and data processing capabilities. The computer processor comprises: a decode unit for decoding instructions; a data processing facility comprising a first data execution path including fixed operators and a second data execution path including at least configurable operators, said configurable operators having a plurality of predefined configurations, at least some of which are selectable by means of an opcode portion of a data processing instruction; wherein said decode unit is operable to detect whether a data processing instruction defines a fixed data processing operation or a configurable data processing operation, said decode unit causing the computer system to supply data for processing to said first data execution path when a fixed data processing instruction is detected and to said configurable data execution path when a configurable data processing instruction is detected.
In further related embodiments, the decode unit may be capable of decoding a stream of instruction packets from memory, each packet comprising a plurality of instructions. The decode unit may also be operable to detect if an instruction packet contains a data processing instruction. The configurable operators may be configurable at the level of multibit values, including multibit values comprising four or more bits, or at the level of words. A plurality of the fixed operators of the first data execution path may be arranged to perform a plurality of fixed operations in independent lanes according to single instruction multiple data principles. Also, a plurality of configurable operators of the second data execution path may be arranged to perform multiple operations in different lanes according to single instruction multiple data principles.
In other related embodiments, configurable operators of the second execution path may be arranged to receive configuration information which determines the nature of the operations performed. This information may be received from a field of an instruction defining a configurable data processing operation. Configurable operators of the second execution path may be arranged to receive configuration information comprising information controlling relative interconnectivity. The computer processor may further comprise a control map associated with configurable operators of the second data execution path, said control map being operable to receive at least one configuration bit from a configurable data processing instruction and to provide configuration information to the configurable operators responsive thereto. The configuration information may determine the nature of the operations performed by said configurable operators; and control interconnectivity between two or more of said configurable operators.
In further related embodiments, configurable operators of the second execution path may be arranged to receive either configuration information determining the nature of an operation to be performed or configuration information controlling interconnectivity from a source other than a configurable data processing instruction. At least one configurable operator of the second data execution path may be capable of executing data processing instructions with an execution depth greater than two computations before returning results to a results store. The computer processor may comprise a switch mechanism for receiving data processing operands from a configurable data processing instruction and switching them as appropriate for supply to one or more of said configurable operators. The computer processor may also comprise a switch mechanism for receiving results from one or more of said configurable operators and switching the results as appropriate for supply to one or more of a result store and feed back loop. The computer processor may also comprise a plurality of control maps for mapping configuration bits received from configurable data processing instructions to configuration information for supply to configurable operators of the second data execution path. Also, the computer processor may comprise a switch mechanism for receiving configuration information from a control map and switching it as appropriate for supply to configurable operators of the second data execution path. The computer processor may also comprise configurable operators selected from one or more of: multiply accumulate operators; arithmetic operators; state operators; and cross-lane permuters. Also, the computer processor may comprise operators and an instruction set capable of performing one or more operations selected from: Fast Fourier Transforms; Inverse Fast Fourier Transforms; Viterbi encoding/decoding; Turbo encoding/decoding; and Finite Impulse Response calculations; and any other Correlations or Convolutions.
In another embodiment according to the invention, there is provided a method of operating a computer processor having control and data processing capabilities, said computer processor comprising a first data execution path including fixed operators and a second data execution path including configurable operators, said configurable operators having a plurality of predefined configurations, at least some of which are selectable by means of an opcode portion of a data processing instruction. The method comprises: decoding a plurality of instructions to detect whether at least one data processing instruction, of said plurality of instructions, defines a fixed data processing operation or a configurable data processing operation; causing the computer processor to supply data for processing to said first data execution path when a fixed data processing instruction is detected and to said configurable data execution path when a configurable data processing instruction is detected; and outputting the results.
In another embodiment according to the invention, there is provided a computer program product comprising program code means for causing a computer processor, said computer processor comprising a first data execution path including fixed operators and a second data execution path including configurable operators, said configurable operators having a plurality of predefined configurations, at least some of which are selectable by means of an opcode portion of a data processing instruction, to: decode a plurality of instructions to detect whether at least one data processing instruction, of said plurality of instructions, defines a fixed data processing operation or a configurable data processing operation; cause the computer processor to supply data for processing to said first data execution path when a fixed data processing instruction is detected and to said configurable data execution path when a configurable data processing instruction is detected; and output the results.
In a further embodiment according to the invention, there is provided a data processing instruction set comprising a first plurality of instructions having a field indicating a fixed type of data processing operation and a second plurality of instructions having a field indicating a configurable type of data processing operations.
In another embodiment according to the invention, there is provided a computer processor having a data execution path comprising configurable operators, wherein the configurable operators comprise a plurality of pre-defined groups of operator configurations, each group comprising operators from a separate operator class. The operator classes may comprise classes selected from one or more of: multiply accumulate operators; arithmetic operators; state operators; and permuters. Connections between operators selected from within each of the pre-defined groups of operator configurations may be capable of being configured by an opcode portion within an instruction executed by the computer processor. Also, connections between operators selected from more than one of the pre-defined groups of operator configurations may be capable of being configured by an opcode portion within an instruction executed by the computer processor.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings; or may be learned by practice of the invention.